1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices and, in particular, to the measurement, determination and monitoring of plasma damage and latent defects in a semiconductor integrated circuit device.
2. Description of the Related Art
Semiconductor integrated circuits are typically fabricated on a wafer or substrate of a semiconductor material such as, for example, silicon or gallium arsenide. During the fabrication, the wafer may be subjected to a sequence of steps, which may include photomasking, material deposition, oxidation, nitridization, ion implantation, diffusion, and etching, among others. Plasma etching is one preferred method for providing etching anisotropy required for a high degree of pattern definition and precise dimensional control in small device geometries. However, as a result of these numerous exposures of the semiconductor substrates to plasma and ionic radiation during the fabrication processes, the substrates may experience excessive radiation damage and accumulation of charge on floating conductive components, which can result in degradation of the gate dielectric and its interfaces.
Early detection and assessment of the accumulation of plasma charge damage in semiconductor devices is a complex problem. A variety of methods have been proposed and explored to address this problem, but with limited success. Of those, the Fowler-Nordheimn uniform tunneling method and hot-carrier stressing method are among the techniques most frequently used for detecting latent damage resulting from process-induced charging events.
In addition, latent defects created by plasma damage pose important reliability problems for the integrated circuit device. These defects are not readily observable by most of the measurement methods commonly used. The latent defects are either passivated defects formed by temperature cycling after defects are created in the integrated circuit, or the latent defects are simply created by charge detrapping that render the defects invisible to many measurements. A common way to reveal these latent defects is to look for accelerated degradation of device parameters under electrical stress. Common stressing methods for detecting this type of defect include the uniform Fowler-Nordheim method and the channel hot-carrier stress method.
The Fowler-Nordheim stressing method forces current to flow through the gate-oxide under high electric field. To evaluate the latent damage to the wafer using Fowler-Nordheim, the wafer is first annealed to detrap all charges and then currents are injected to repopulate the discharged traps. By measuring the post Fowler-Nordheim stress, transistor threshold voltage (Vt) and transconductance (Gm) shifts caused by plasma damage is assessed by comparing the damaged device to a control device or by detecting antenna ratio dependency in the device.
An additional use of the Fowler-Nordheim stress to measure plasma-damage is to monitor the voltage required for maintaining a constant current injection through a gate oxide. The Initial Electron Trapping Rate (IETR) can be measured from the resultant voltage curve. The IETR is proportional to the electron trap density in the oxide under test. Electron trap density is, in turn, an indicator of plasma damage.
A second type of stress testing method for integrated circuits is the hot-carrier or hot-electron stress method. Although both Fowler-Nordheim and hot-carrier methods detect plasma and latent damage, hot-carrier stress is more sensitive and more adequately quantifies the effect of process-induced events. The hot-carrier stress for n-MOSFET typically place the device at a high drain bias with a gate bias that maximizes the substrate current for a short duration of time. The conditions are set such that a normal, undamaged device is degraded by at least 3 to 5%, as measured on a production tester.
The conventional hot-carrier stress method to determine the lifetime of transistors under nominal operating condition involves aging the device under mildly accelerated conditions for a long period of time. To speed things up, often the aging for each voltage condition is not carried to the point the device degrades beyond the lifetime specification (10% peak linear transconductance (Gm) degradation, for n-channel device, for example). Instead, aging is stopped after a sufficient time and the lifetime for that particular aging condition is obtained through extrapolation. This extrapolation is made possible by the power-law relationship between interface-states generation (xcex94Nit) (the main degradation mechanism for n-channel devices) and stress time t:
xcex94Nit=tnxe2x80x83xe2x80x83(1)
Since interface states affect Gm by reducing the carrier mobility, Gm degradation follows the power-law:
xcex94Gm=Atnxe2x80x83xe2x80x83(2)
where A is a constant.
In other words, a plot of log (xcex94Gm/Gm) versus log(t) produces a straight line that can be used for the purpose of extrapolation.
The reason that a stress must be carried out to a long enough time is that there is a saturation effect in the generation rate of interface states. Only after the degradation rate (slope of the curve) of Gm reaches the asymptotic value can one fit the data in the log-log plot to a straight line for lifetime extrapolation. FIG. 1 shows an example of the saturation behavior and the linear extrapolation method for lifetime extraction.
Since plasma-damage is a high-field stressing phenomenon, the most prominent characteristic of degradation is in the increase of fluctuation for most electrical parameters for a device. It is therefore important to measure the degradation of a large enough number of devices to ensure good statistics. This requirement rules out any time consuming methods to be used on a routine basis. Channel hot-carrier stress is therefore normally not a suitable stress method for plasma damage monitoring.
For the purpose of monitoring plasma damage, the absolute hot-carrier lifetime for the devices is not needed. One only need to compare the lifetime under the same accelerated aging condition to see if it is degraded by damage. In principle, the ratio of change in accelerated lifetime due to damage should have a one-to-one relationship to the lifetime change at operating condition.
The prior art overcame the long stress time requirement by using a much higher than normal acceleration voltage to stress the transistors. Hook et al., xe2x80x9cA Comparison of Hot-Electron and Fowler-Nordheim Characterization of Charging Events in a 0.5 m CMOS Technologyxe2x80x9d, 164 International Symposium on Plasma Process-Induced Damage, 1996, for example, chose the stress voltage such that in 5 seconds of aging time, 3% to 5% of Gm degradation would occur. As shown in FIG. 1, the 3% to 5% level of degradation is high enough that most of the time the device degradation rate has already reached the asymptotic value. By using such a high level of acceleration, the stress time was cut down to 5 seconds per device, allowing this method to be used with good enough statistics.
In order to further shorten the stress time to speed measurement according to the prior art methods, stress conditions would have to be increased even further. While there is no proof that such a practice will produce erroneous results, the ultra high stress voltage that would be required to speed measurement has been avoided due to the lack of a established voltage acceleration model.
The present invention overcomes the drawbacks of the prior art and provides a method for determining the presence of plasma damage and latent defects while shortening the time for hot-carrier stress and without using an unusually high stress voltage.
The present invention is a method for shortening the time for hot-carrier stress without using unusually high stress voltage. By using the early part of the degradation curve ((logxcex94Gm/Gm)/log(t)), before the slope reaches the asymptotic value, the interface state generation (Nit) may be expressed in terms of interface state creation efficiency (K). For a given gate-oxide type and quality, interface state creation efficiency (K) is a constant while the channel engineering of the transistor and the channel length determines the time dependent impact ionization rate. As set forth in more detail below, the degradation curve includes two components: an intrinsic component and a damage-induced component. Because the ratio of these two components remains the same throughout the curve, as long as the transistor design remains the same, the damage-induced change of the xcex94Gm/Gm at any part of the degradation curve will have a one-to-one relationship with the extrapolated lifetime change. The change in the transconductance as a function of time, i.e., the slope of the degradation curve, is measured and then compared to a reference value. Thus, the method of the present invention allows the use of hot-carrier stress in a time efficient manner without the need of applying very high acceleration voltages.